A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS

• Published in: IEEE journal of solid-state circuits Vol. 56; no. 1; pp. 287 - 297
• Main Authors: Liu, Hui, Xing, Xinpeng, Gielen, Georges
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital conversion; Analog to digital converters; Approximation; b/cycle asynchronous successiveapproximation-register (ASAR); Calibration; CMOS; continuous-time (CT) ΔΣ analog-to-digital converter (ADC); Digital to analog conversion; Digital to analog converters; Feedforward systems; flat signal transfer function (STF); Gain; Linearity; Noise; Noise levels; Noise reduction; noise-shaping (NS) QTZ; on-chip digital-to-analog converter (DAC) calibration; out-of-band blocker (OBB); Power consumption; Steering; System-on-chip; Topology; Transfer functions; Wireless communication systems; Wireless communications
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2020.3005817

This article presents a continuous-time (CT) <inline-formula> <tex-math notation="LaTeX">\Delta \Sigma </tex-math></inline-formula> analog-to-digital converter for wireless communication systems with a high tolerance against blockers. The zero-cancellation technique is introduced to eliminate the peaking in the signal transfer function (STF) to achieve better out-of-band-blocker immunity. An on-chip unary-approximating calibration is implemented to calibrate the mismatch of the outer current-steering digital-to-analog converter. A discrete-time (DT) second-order noise-shaping (NS) 2b/cycle asynchronous successive-approximation-register (ASAR) quantizer further reduces the quantization noise and the excess loop delay, achieving a CT-DT hybrid sixth-order NS without suffering from neither the problem of the CT-DT transfer function matching in a CT multistage NS topology nor the stability issue in a single-loop fully CT sixth-order topology. The prototype is fabricated in 28-nm bulk CMOS and is clocked at 1.7 GHz. With a bandwidth of 85 MHz, the analog-to-digital converter achieves 0-dB peaking STF, 74.4-dB signal to noise and SNDR and 87.5-dB spurious-free dynamic range, while consuming 61.8-mW power, resulting in an excellent Schreier Figure-of-Merit (FoM<inline-formula> <tex-math notation="LaTeX">_{S} </tex-math></inline-formula>) of 165.8 dB.