3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor

• Published in: IEEE journal of solid-state circuits Vol. 29; no. 3; pp. 298 - 302
• Main Authors: Murabayashi, F., Hotta, T., Tanaka, S., Yamauchi, T., Yamada, H., Nakano, T., Kobayashi, Y., Bandoh, T.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.03.1994; Institute of Electrical and Electronics Engineers
• Subjects: Adders; Applied sciences; BiCMOS integrated circuits; Bipolar transistors; CMOS technology; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Logic circuits; Low voltage; Microprocessors; MOSFETs; Reduced instruction set computing; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Wiring; Circuit architecture; BiCMOS technology; Circuit design; Integrated circuit; Floating point; Microprocessor; Fast circuit
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.278351

This paper describes 3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. The processor is implemented in a 0.5-/spl mu/m BiCMOS technology with 4-metal-layer structure. The chip includes a 240 MFLOPS fully pipelined 64-b floating point datapath, a 240-MIPS integer datapath, and 24 KB cache, and contains 2.8 million transistors. The processor executes up to four operations at 120 MHz and dissipates 17 W. Novel BiCMOS circuits, such as a 0.6-ns single-ended common base sense amplifier, a 0.46-ns 22-b comparator, and a 0.7-ns path logic adder are applied to the processor. The processor with the proposed BiCMOS circuits has a 11%-47% shorter delay time advantage over a CMOS microprocessor.< >