An Area-Efficient Majority Logic-Based Approximate Adders with Low Delay for Error-Resilient Applications

• Published in: Circuits, systems, and signal processing Vol. 41; no. 9; pp. 4977 - 4997
• Main Authors: Parameshwara, M. C., Maroof, Naeem
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.09.2022; Springer Nature B.V
• Subjects: Adding circuits; Cellular automata; Circuits and Systems; Delay; Design; Electrical Engineering; Electronics and Microelectronics; Engineering; Image processing; Image quality; Instrumentation; Signal,Image and Speech Processing; Error-tolerant; Approximate adder; QCA; Majority logic

This paper presents two new inexact sum-based 1-bit approximate full adders (AFAs). The proposed 1-bit approximate adders (PAAs), namely PAA1 and PAA2, are derived based on the majority logic. The layouts of PAAs are designed in quantum cellular automata (QCA) technology using the QCADesigner tool....