An Area-Efficient Majority Logic-Based Approximate Adders with Low Delay for Error-Resilient Applications
This paper presents two new inexact sum-based 1-bit approximate full adders (AFAs). The proposed 1-bit approximate adders (PAAs), namely PAA1 and PAA2, are derived based on the majority logic. The layouts of PAAs are designed in quantum cellular automata (QCA) technology using the QCADesigner tool....
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| Published in | Circuits, systems, and signal processing Vol. 41; no. 9; pp. 4977 - 4997 |
|---|---|
| Main Authors | , |
| Format | Journal Article |
| Language | English |
| Published |
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Springer US
01.09.2022
Springer Nature B.V |
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| Abstract | This paper presents two new inexact sum-based 1-bit approximate full adders (AFAs). The proposed 1-bit approximate adders (PAAs), namely PAA1 and PAA2, are derived based on the majority logic. The layouts of PAAs are designed in quantum cellular automata (QCA) technology using the QCADesigner tool. To assess the performance of PAAs, we compare them against the reported AFAs in terms of various design metrics, such as the total area, delay, and performance. The comparison results show that the PAA1 and PAA2, having an area of 0.02
μ
m
2
and 0.04
μ
m
2
, provide area savings of 60% and 20%, respectively, compared with the lowest-area AFA reported in the literature. Also, the PAA1 and PAA2 have an equal delay of 0.5 clock cycles, that is, 33.33% less as compared to the AFA with the lowest delay. The designs are analyzed in terms of image quality metrics for image processing applications. Besides area efficiency and delay performance, on average, PAA1 provides the worst PSNR/SNR, while PAA2 provides the best PSNR/SNR compared to the other state-of-the-art approximate adders. |
|---|---|
| AbstractList | This paper presents two new inexact sum-based 1-bit approximate full adders (AFAs). The proposed 1-bit approximate adders (PAAs), namely PAA1 and PAA2, are derived based on the majority logic. The layouts of PAAs are designed in quantum cellular automata (QCA) technology using the QCADesigner tool. To assess the performance of PAAs, we compare them against the reported AFAs in terms of various design metrics, such as the total area, delay, and performance. The comparison results show that the PAA1 and PAA2, having an area of 0.02
μ
m
2
and 0.04
μ
m
2
, provide area savings of 60% and 20%, respectively, compared with the lowest-area AFA reported in the literature. Also, the PAA1 and PAA2 have an equal delay of 0.5 clock cycles, that is, 33.33% less as compared to the AFA with the lowest delay. The designs are analyzed in terms of image quality metrics for image processing applications. Besides area efficiency and delay performance, on average, PAA1 provides the worst PSNR/SNR, while PAA2 provides the best PSNR/SNR compared to the other state-of-the-art approximate adders. This paper presents two new inexact sum-based 1-bit approximate full adders (AFAs). The proposed 1-bit approximate adders (PAAs), namely PAA1 and PAA2, are derived based on the majority logic. The layouts of PAAs are designed in quantum cellular automata (QCA) technology using the QCADesigner tool. To assess the performance of PAAs, we compare them against the reported AFAs in terms of various design metrics, such as the total area, delay, and performance. The comparison results show that the PAA1 and PAA2, having an area of 0.02 μm2 and 0.04 μm2, provide area savings of 60% and 20%, respectively, compared with the lowest-area AFA reported in the literature. Also, the PAA1 and PAA2 have an equal delay of 0.5 clock cycles, that is, 33.33% less as compared to the AFA with the lowest delay. The designs are analyzed in terms of image quality metrics for image processing applications. Besides area efficiency and delay performance, on average, PAA1 provides the worst PSNR/SNR, while PAA2 provides the best PSNR/SNR compared to the other state-of-the-art approximate adders. |
| Author | Maroof, Naeem Parameshwara, M. C. |
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| Cites_doi | 10.1109/WiSPNET.2016.7566219 10.1088/0957-4484/4/1/004 10.1109/TNANO.2011.2158006 10.1109/TENCON.2011.6129222. 10.1109/TNANO.2003.820815 10.1109/ISCAS.2018.8350962 10.1109/ISCAS.2017.8050819 10.1109/NANO.2003.1231818 10.1142/S0218126621502352 10.1109/ISSCC.2016.7417888 10.3850/9783981537079_0042 10.1109/MSPEC.2016.7551335 10.1109/92.974895 10.1021/ja026856g 10.1109/TCSI.2009.2027626 10.1063/1.356375 10.1109/MCD.2005.1388765 10.1145/3232195.3232216 10.1109/NANO.2006.247647 10.1109/TVLSI.2018.2822278 10.1109/ICCT.2008.4716260 10.1109/TC.2009.21 |
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| References | RairighDLimits of CMOS Technology Scaling and Technologies Beyond-CMOS2005PiscatawayInstitute of Electrical and Electronics Inc. B. Aravinth, L.J.A. Marcilin, Implementation of coplanar approximate adders in QCA, in 2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), pp. 680–684 (2016) W.M. Holt: 1.1 Moore’s law: a path going forward, in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 8–13 (2016). https://doi.org/10.1109/ISSCC.2016.7417888 PudiVSridharanKLow complexity design of ripple Carry and Brent-Kung adders in QCAIEEE Trans. Nanotechnol.201211110511910.1109/TNANO.2011.2158006 LentCSTougawPDPorodWBernsteinGHQuantum cellular automataNanotechnology19934495710.1088/0957-4484/4/1/004 M.C. Parameshwara, Approximate full adders for energy efficient image processing applications. J. Circuits Syst. Comput. 30(13) (early access) DallooANajafiAGarcia-OrtizASystematic design of an approximate adder: the optimized lower part constant-OR adderIEEE Trans. Very Large Scale Integr. (VLSI) Syst.20182681595159910.1109/TVLSI.2018.2822278 ChoHSwartzlanderEEAdder and multiplier design in quantum-dot cellular automataIEEE Trans. Comput.2009586721727267520110.1109/TC.2009.21 TougawPDLentCSLogical devices implemented using quantum cellular automataJ. Appl. Phys.19947531818182410.1063/1.356375 HegdeRShanbhagNRSoft digital signal processingIEEE Trans. Very Large Scale Integr. (VLSI) Syst.20019681382310.1109/92.974895 B. Sen, T. Adak, A.S. Anand, B.K. Sikdar, Synthesis of reversible universal QCA gate structure for energy efficient digital design, in TENCON 2011—2011 IEEE Region 10 Conference, Bali, 2011, pp. 806–810. https://doi.org/10.1109/TENCON.2011.6129222. ZareeiZNaviKKeshavarziyanPLow-power, high-speed 1-bit inexact full adder cell designs applicable to low-energy image processingInt. J. Electron.20181053375384 LentCSIsaksenBLiebermanMMolecular quantum-dot cellular automataJ. Am. Chem. Soc.200312541056106310.1021/ja026856g V. Vankamamidi, M. Ottavi, F. Lombardi, Clocking and cell placement for QCA, in Sixth IEEE Conference on Nanotechnology, 2006, pp. 343–346 (2006) R. Courtland, Transistors could stop shrinking in 2021: a key industry report forecasts an end to traditional scaling of transistors, IEEE Spectrum (2016). https://spectrum.ieee.org/semiconductors/devices/transistors-could-stop-shrinking-in-2021 SkotnickiTHutchbyJATsu-Jae KingH-PWongF. BoeufThe end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performanceIEEE Circuits and Devices Magazine2005211162610.1109/MCD.2005.1388765 MahdianiHRAhmadiAFakhraieSMLucasCBio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applicationsIEEE Trans. Circuits Syst. I Regul. Pap.2010574850862275668010.1109/TCSI.2009.2027626 W. Wang, K. Walus, G.A. Jullien, Quantum-dot cellular automata adders, in 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003., San Francisco, CA, USA, 2003, vol. 2, pp. 461–464 AraniIERezaiANovel circuit design of serial-parallel multiplier in quantum-dot cellular automata technologyJ. Comput. Electron.2018719 C. Labrado, H. Thapliyal, F. Lombardi, Design of majority logic based approximate arithmetic circuits, in IEEE International Symposium on Circuits and Systems (ISCAS), 2017, pp. 1–4 (2017) K. Walus, A. Vetteth, G. Jullien, V. Dimitrov, RAM design using quantum-dot cellular automata, in Tech Proceedings of Nanotechnology Conference and Trade Show2, 160–163 (2003) WalusKDysartTJJullienGABudimanRAQCADesigner: a rapid design and Simulation tool for quantum-dot cellular automataIEEE Trans. Nanotechnol.200431263110.1109/TNANO.2003.820815 Y. Xia, K. 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Lombardi, Inexact designs for approximate low power addition by cell replacement, in Proceedings of IEEE International Conference on Design, Automation and Test in Europe Conference and Exhibition (DATE), Dresden, Germany, pp. 660–665 (2016) O. Liolis, V.A. Mardiris, G.C. Sirakoulis, I.G. Karafyllidis: Quantum-dot cellular automata RAM design using crossbar architecture, in IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). 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| References_xml | – reference: V. Vankamamidi, M. Ottavi, F. Lombardi, Clocking and cell placement for QCA, in Sixth IEEE Conference on Nanotechnology, 2006, pp. 343–346 (2006) – reference: M.C. Parameshwara, Approximate full adders for energy efficient image processing applications. J. Circuits Syst. Comput. 30(13) (early access) – reference: TougawPDLentCSLogical devices implemented using quantum cellular automataJ. Appl. Phys.19947531818182410.1063/1.356375 – reference: ChoHSwartzlanderEEAdder and multiplier design in quantum-dot cellular automataIEEE Trans. Comput.2009586721727267520110.1109/TC.2009.21 – reference: PudiVSridharanKLow complexity design of ripple Carry and Brent-Kung adders in QCAIEEE Trans. Nanotechnol.201211110511910.1109/TNANO.2011.2158006 – reference: WalusKDysartTJJullienGABudimanRAQCADesigner: a rapid design and Simulation tool for quantum-dot cellular automataIEEE Trans. Nanotechnol.200431263110.1109/TNANO.2003.820815 – reference: K. Walus, A. Vetteth, G. Jullien, V. Dimitrov, RAM design using quantum-dot cellular automata, in Tech Proceedings of Nanotechnology Conference and Trade Show2, 160–163 (2003) – reference: International Road Map for Devices and Systems (IRDS): Beyond CMOS, 2020 Edition, available at https://irds.ieee.org/images/files/pdf/2020/2020IRDS_MM.pdf – reference: R. Courtland, Transistors could stop shrinking in 2021: a key industry report forecasts an end to traditional scaling of transistors, IEEE Spectrum (2016). https://spectrum.ieee.org/semiconductors/devices/transistors-could-stop-shrinking-in-2021 – reference: HegdeRShanbhagNRSoft digital signal processingIEEE Trans. Very Large Scale Integr. (VLSI) Syst.20019681382310.1109/92.974895 – reference: http://www.imageprocessingplace.com – reference: SkotnickiTHutchbyJATsu-Jae KingH-PWongF. BoeufThe end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performanceIEEE Circuits and Devices Magazine2005211162610.1109/MCD.2005.1388765 – reference: H.A.F. Almurib, T.N. Kumar, F. Lombardi, Inexact designs for approximate low power addition by cell replacement, in Proceedings of IEEE International Conference on Design, Automation and Test in Europe Conference and Exhibition (DATE), Dresden, Germany, pp. 660–665 (2016) – reference: W.M. Holt: 1.1 Moore’s law: a path going forward, in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 8–13 (2016). https://doi.org/10.1109/ISSCC.2016.7417888 – reference: LentCSTougawPDPorodWBernsteinGHQuantum cellular automataNanotechnology19934495710.1088/0957-4484/4/1/004 – reference: O. Liolis, V.A. Mardiris, G.C. Sirakoulis, I.G. Karafyllidis: Quantum-dot cellular automata RAM design using crossbar architecture, in IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). Athens, 2018, pp. 1–5 (2018) – reference: DallooANajafiAGarcia-OrtizASystematic design of an approximate adder: the optimized lower part constant-OR adderIEEE Trans. Very Large Scale Integr. (VLSI) Syst.20182681595159910.1109/TVLSI.2018.2822278 – reference: C. Labrado, H. Thapliyal, F. Lombardi, Design of majority logic based approximate arithmetic circuits, in IEEE International Symposium on Circuits and Systems (ISCAS), 2017, pp. 1–4 (2017) – reference: MahdianiHRAhmadiAFakhraieSMLucasCBio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applicationsIEEE Trans. Circuits Syst. I Regul. Pap.2010574850862275668010.1109/TCSI.2009.2027626 – reference: RairighDLimits of CMOS Technology Scaling and Technologies Beyond-CMOS2005PiscatawayInstitute of Electrical and Electronics Inc. – reference: LentCSIsaksenBLiebermanMMolecular quantum-dot cellular automataJ. Am. Chem. Soc.200312541056106310.1021/ja026856g – reference: R. Zhang, K. Walus, W. Wang, G.A. Jullien, Performance comparison of quantum-dot cellular automata adders, in 2005 IEEE International Symposium on Circuits and Systems, Kobe, 2005, vol. 3, pp. 2522–2526 – reference: B. Aravinth, L.J.A. Marcilin, Implementation of coplanar approximate adders in QCA, in 2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), pp. 680–684 (2016) – reference: Y. Xia, K. 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| Snippet | This paper presents two new inexact sum-based 1-bit approximate full adders (AFAs). The proposed 1-bit approximate adders (PAAs), namely PAA1 and PAA2, are... |
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| SubjectTerms | Adding circuits Cellular automata Circuits and Systems Delay Design Electrical Engineering Electronics and Microelectronics Engineering Image processing Image quality Instrumentation Signal,Image and Speech Processing |
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| Title | An Area-Efficient Majority Logic-Based Approximate Adders with Low Delay for Error-Resilient Applications |
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