Searching for complete set of free resource rectangles on FPGA area based on CPTR

As a coprocessor, field-programmable gate array （FPGA） is the hardware computing processor accelerating the computing capacity of coraputers. To efficiently manage the hardware free resources for the placing of tasks on FPGA and take full advantage of the partially reconfigurable units, good utiliza...

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Bibliographic Details
Published inJournal of Shanghai University Vol. 15; no. 5; pp. 391 - 396
Main Author 柴亚辉 沈文枫 徐炜民 刘觉夫 郑衍衡
Format Journal Article
LanguageEnglish
Published Heidelberg Shanghai University Press 01.10.2011
School of Information Engineering, East China Jiaotong University, Nanchang 330013, P.R.China%School of Computer Engineering and Science, Shanghai University, Shanghai 200072, P.R.China%School of Information Engineering, East China Jiaotong University, Nanchang 330013, P.R.China
School of Computer Engineering and Science, Shanghai University, Shanghai 200072, P.R.China
Subjects
Classical Mechanics
Computation
Engineering
Environment
Field programmable gate arrays
FPGA
Hardware
Information Technology
Life Sciences
Materials Science
Mathematical and Computational Engineering
Mechatronics
Microprocessors
Placing
Rectangles
Running
Tasks
免费资源
协处理器
基础
搜索
现场可编程门阵列
矩形
计算能力
maximal free rectangle
occupied rectangle
field-programmable gate array (FPGA)
partially dynamic reconfigure
field-programmable gate array(FPGA)
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Summary:As a coprocessor, field-programmable gate array （FPGA） is the hardware computing processor accelerating the computing capacity of coraputers. To efficiently manage the hardware free resources for the placing of tasks on FPGA and take full advantage of the partially reconfigurable units, good utilization of chip resources is an important and necessary work. In this paper, a new method is proposed to find the complete set of maximal free resource rectangles based on the cross point of edge lines of running tasks on FPGA area, and the prove process is provided to make sure the correctness of this method.
Bibliography:CHAI Ya-hui , SHEN Wen-feng , XU Wei-min, LIU Jue-fu, ZHENG Yan-heng（1. School of Computer Engineering and Science, Shanghai University, Shanghai 200072, P. R. China; 2. School of Information Engineering, East China Jiaotong University, Nanchang 330013, P. R. China）
field-programmable gate array （FPGA）, partially dynamic reconfigure, maximal free rectangle, occupied rectangle
As a coprocessor, field-programmable gate array （FPGA） is the hardware computing processor accelerating the computing capacity of coraputers. To efficiently manage the hardware free resources for the placing of tasks on FPGA and take full advantage of the partially reconfigurable units, good utilization of chip resources is an important and necessary work. In this paper, a new method is proposed to find the complete set of maximal free resource rectangles based on the cross point of edge lines of running tasks on FPGA area, and the prove process is provided to make sure the correctness of this method.
31-1735/N
ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISSN:1007-6417
1863-236X
DOI:10.1007/s11741-011-0757-2