Electrical Characterisation of Thick 3C-SiC Layers Grown on Off-Axis 4H-SiC Substrates

300 μm thick 3C-SiC epilayer was grown on off-axis 4H-SiC(0001) substrate with a high growth rate of 1 mm/hour. Dry oxidation, wet oxidation and N2O anneal were applied to fabricate lateral MOS capacitors on these 3C-SiC layers. MOS interface obtained by N2O anneal has the lowest interface trap dens...

Full description

Saved in:
Bibliographic Details
Published inMaterials science forum Vol. 963; pp. 353 - 356
Main Authors Sharma, Yogesh, Jokubavicius, Valdas, Russell, Stephen, La Via, Francesco, Jennings, Michael R., Mawby, Philip Andrew, Yakimova, Rositza, Pérez Tomás, Amador, Li, Fan, Roccaforte, Fabrizio
Format Journal Article
LanguageEnglish
Published Pfaffikon Trans Tech Publications Ltd 19.07.2019
Subjects
Annealing
Capacitors
Charge density
Nitrous oxide
Oxidation
Substrates
Wet oxidation
Sublimation Epitaxy
Interface Trap Density
3C-SiC
Gate Oxidation
Online AccessGet full text

Cover

More Information
Summary:300 μm thick 3C-SiC epilayer was grown on off-axis 4H-SiC(0001) substrate with a high growth rate of 1 mm/hour. Dry oxidation, wet oxidation and N2O anneal were applied to fabricate lateral MOS capacitors on these 3C-SiC layers. MOS interface obtained by N2O anneal has the lowest interface trap density of 3~4x1011 eV-1cm-2. Although all MOS capacitors still have positive net charges at the MOS interface, the wet oxidised sample has the lowest effective charge density of ~9.17x1011 cm-2.
Bibliography:Selected, peer reviewed papers from the European Conference on Silicon Carbide and Related Materials (ECSCRM 2018), September 2-6, 2018,Birmingham, UK
ISSN:0255-5476
1662-9752
1662-9752
DOI:10.4028/www.scientific.net/MSF.963.353