High-Current Switched Capacitor Converter for On-Package VR With PDN Impedance Modeling

Digital ASIC devices are widely used in networking and computing applications. This kind of devices is implemented with a short-channel technology requiring high peak currents for high complexity systems and a low supply voltage. Digital ASICs are powered by an external voltage regulator with specif...

Full description

Saved in:
Bibliographic Details
Published inIEEE journal of emerging and selected topics in power electronics Vol. 8; no. 2; pp. 1633 - 1643
Main Authors Ursino, Mario, Saggini, Stefano, Jiang, Shuai, Nan, Chenhao, Rinaldo, Roberto, Rizzolatti, Roberto
Format Journal Article
LanguageEnglish
Published Piscataway IEEE 01.06.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Online AccessGet full text

Cover

Loading…
More Information
Summary:Digital ASIC devices are widely used in networking and computing applications. This kind of devices is implemented with a short-channel technology requiring high peak currents for high complexity systems and a low supply voltage. Digital ASICs are powered by an external voltage regulator with specifications similar to modern microprocessors' power supply [voltage regulation modules (VRMs)]. In order to reduce the number of power pins and to reduce the power distribution network (PDN) issue, Intel's Fourth-Generation Core integrates the voltage regulators. Moreover, many on-package conversion systems are present in the literature. In this article, a conversion solution based on a switched resonant tank is presented, yielding currents up to 300 A at 0.8 V, in an area of 10 cm 2 , with a resonant-driving technique. The novel converter is used to validate a new linear time-periodic (LTP) system modeling approach that can be applied to generic switched topologies; this contribution yields a mathematical description of the conversion chain, in particular enabling the precise calculation of the output impedance when a switched topology is used as the last stage.
ISSN:2168-6777
2168-6785
DOI:10.1109/JESTPE.2019.2942969