Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems Perspective

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 43; no. 10; pp. 2840 - 2853
• Main Authors: Kai-Chun Chang, Kevin, Liu, Guan-Ting, Chiang, Chun-Yao, Lee, Pei-Yu, Hui-Ru Jiang, Iris
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accuracy; Adaptation models; Analytical models; Collaboration; Corners; Filtration; Integrated circuit modeling; Libraries; Matrix completion; Modelling; multiple corners; Performance degradation; Pins; recommendation systems; Recommender systems; Timing; timing macro modeling; Training
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2024.3383350

Timing macro modeling has been widely employed to enhance the efficiency and accuracy of parallel and hierarchical timing analysis. However, existing studies primarily focused on generating an accurate and compact timing macro model for single-corner libraries, making it difficult to adapt these approaches to multi-corner situations. This either incurs substantial engineering effort or results in significant performance degradation. To tackle this challenge, we offer a fresh perspective on the timing macro modeling problem by drawing inspiration from recommendation systems and formulating it as a matrix completion task. We propose a neural collaborative filtering-based framework capable of capturing the convoluted relationships between circuit pins and timing corners. This framework enables the precise identification of timing variant regions across different corners. Additionally, we design several training features and implement various training techniques to enhance precision. Experimental results show that our framework reduces model sizes by more than 10% compared to state-of-the-art single-corner approaches, while maintaining competitive timing accuracy and exhibiting significant runtime improvements. Furthermore, when applied to unseen corners, our framework consistently delivers superior performance, demonstrating its potential for use in off-corner chiplets in a heterogeneous integration system.