An Intrinsically Linear 13-Level Capacitive DAC for Delta Sigma Modulators

Mismatch of the digital-to-analog converter (DAC) elements is the major limitation for Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) in multi-bit Delta Sigma Modulators (DSM). In this brief we extend a previously introduced technique to build an intrinsically lin...

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Bibliographic Details
Published inIEEE transactions on circuits and systems. II, Express briefs Vol. 70; no. 4; pp. 1291 - 1295
Main Authors Dalla Longa, Matteo, Conzatti, Francesco, Hofmann, Tobias, Kauffman, John G., Ortmanns, Maurits
Format Journal Article
LanguageEnglish
Published New York IEEE 01.04.2023
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
ADC
Capacitors
Circuits
Codes
DAC
Delta Sigma
Digital to analog converters
Linearity
Modulation
Modulators
multibit
Quantization (signal)
Switches
Tail
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Summary:Mismatch of the digital-to-analog converter (DAC) elements is the major limitation for Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) in multi-bit Delta Sigma Modulators (DSM). In this brief we extend a previously introduced technique to build an intrinsically linear 13 level DAC. An exemplary Switched-Capacitor (SC) 13-levels 20 kHz discrete-time DSM employing this technique is simulated and achieves an SFDR higher than 100 dBc on circuit level in presence of considerable capacitor mismatch. The presented DAC architecture is not limited to be used in a discrete-time modulator, but could also be employed in a Continuous-Time DSM (CTDSM).
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2022.3224878