Statistical Post-FEC BER Estimation of High-Speed Serial Links Subject to DFE Error Propagation

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 72; no. 4; pp. 1888 - 1901
• Main Authors: Chen, Zhuo, Song, Kezhu, Zhu, Chengyang, Zou, Dongwei, Xu, Yuecheng
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2025; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analytical models; Bit error rate; block codes; Codes; Computation; Computational modeling; Decision feedback equalizers; Errors; Estimation; Forward error correction; High speed; Markov chains; Markov processes; Steady-state; Symbols; Vectors
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2024.3491191

This paper proposes a novel and efficient model for the estimation of post-FEC BER for high-speed serial links using FEC codes such as RS (544, 514) in the presence of DFE error propagation. The model employs the Markov model for DFE error propagation and incorporates concepts from the Gilbert-Elliott model. Using various optimization techniques, including Markov state aggregation, burst tables, and adaptive neglect of rare cases, it achieves a computation time that is only 1.658% of that required by previous work for the post-FEC BER computation with RS (544, 514) FEC code and a 2-tap DFE. Furthermore, analyses demonstrate that its computation time increases less rapidly with respect to the number of DFE taps compared to previous works, indicating its better applicability for systems with more DFE taps or larger state spaces. Data measured from an FPGA-based behavior simulator proved that the model can accurately estimate post-FEC BER.