Improved Ferroelectric/Semiconductor Interface Properties in Hf0.5Zr0.5O2 Ferroelectric FETs by Low-Temperature Annealing

• Published in: IEEE electron device letters Vol. 41; no. 10; pp. 1588 - 1591
• Main Authors: Toprasertpong, Kasidit, Tahara, Kento, Fukui, Taichiro, Lin, Zaoyang, Watanabe, Kouhei, Takenaka, Mitsuru, Takagi, Shinichi
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Annealing; Capacitance-voltage characteristics; Capacitors; Crystallization; ferroelectric FET (FeFET); Ferroelectric materials; Ferroelectricity; Field effect transistors; Hafnium oxide; Hf₀․₅Zr₀․₅O; High temperature; interfacial layer; Interfacial properties; Logic gates; Low temperature; MOS interface; Silicon; Temperature; Thin films
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2020.3019265

Crystallization annealing is a key process for the formation of the ferroelectric phase in HfO 2 -based ferroelectric thin films. In this study, we systematically investigate the notable tradeoff of the annealing process, with temperature varied from 300°C to 700°C, on the Hf 0.5 Zr 0.5 O 2 /Si interface properties of ferroelectric FETs. While high-temperature annealing leads to improved ferroelectricity, it results in the unintentional formation of an interfacial layer and the increased interface state density. Ferroelectric FETs prepared with high annealing temperature consequently show degraded subthreshold swing, decreased memory window, and increased OFF current. Our results suggest that annealing ferroelectric FETs at temperature as low as possible for sufficient ferroelectricity, which is 400°C in this study, is an effective approach to improve the device performance of Hf 0.5 Zr 0.5 O 2 ferroelectric FETs.