Electrical Degradation and Recovery of Low-Temperature Polycrystalline-Silicon Thin-Film Transistors With Various Metal Gate Patterns

• Published in: IEEE transactions on electron devices Vol. 59; no. 12; pp. 3543 - 3548
• Main Authors: CHANG, Jiun-Jye, CHANG-LIAO, Kuei-Shu, LI, Chen-Chien
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.12.2012; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Electronics; Exact sciences and technology; Insulators; Logic gates; Low-temperature polycrystalline-silicon (LTPS) thin-film transistors (TFTs) (LTPS TFTs); Metals; plasma process-induced damage (PPID); Plasmas; positive bias temperature instability (PBTI); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Thin film transistors; Threshold voltage; Transistors; Thermal stress; Bias temperature instability; Metallic bond; Polycrystal; Plasma assisted processing; Contact line; Degradation; Low-temperature polycrystalline-silicon (LTPS) thin-film transistors (TFTs) (LTPS TFTs); Leakage current; Silicon; Thin film transistor; Reliability; plasma process-induced damage (PPID); positive bias temperature instability (PBTI); Low temperature; Damaging; Passivation
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2012.2219053

The plasma process-induced damage (PPID) of low-temperature polycrystalline-silicon (LTPS) thin-film transistors (TFTs) (LTPS TFTs) during metal gate manufacturing is studied in this work. Different metal gate architecture configurations were designed to reduce metal line resistance, optimize TFT driving ability, and suppress TFT leakage current by increasing metal gate thickness, modifying the TFT channel width/length, and adopting dual-gate TFT structure, respectively. Experimental results indicate the relationship of the degradation and reliability of TFT with different metal gate designs after positive-bias-temperature-instability stressing. Recovery effects against process damages are also demonstrated by post-etch treatments and gate dielectric modification. The trap-state densities are measured to investigate the PPID effects due to metal gate patterning and the passivation effects after different treatments.