Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator

• Published in: IEEE computer architecture letters Vol. 23; no. 1; pp. 112 - 116
• Main Authors: Luo, Haocong, Tugrul, Yahya Can, Bostanc, F. Nisa, Olgun, Ataberk, Yaglkc, A. Giray, Mutlu, Onur
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: C++ languages; Codes; Computer architecture; computer simulation systems engineering and theory; computers and information processing; Control systems design; Controllers; DRAM systems engineering and theory; Dynamic random access memory; Extensibility; memory; memory architecture computers and information processing; memory management computers and information processing; modeling; Modularity; Organizations; Random access memory; scalability; Simulation; Simulators; Software architecture; system analysis and design; System reliability; system simulation systems engineering and theory; Timing
• ISSN: 1556-6056; 1556-6064
• DOI: 10.1109/LCA.2023.3333759

We present Ramulator 2.0, a highly modular and extensible DRAM simulator that enables rapid and agile implementation and evaluation of design changes in the memory controller and DRAM to meet the increasing research effort in improving the performance, security, and reliability of memory systems. Ramulator 2.0 abstracts and models key components in a DRAM-based memory system and their interactions into shared interfaces and independent implementations . Doing so enables easy modification and extension of the modeled functions of the memory controller and DRAM in Ramulator 2.0. The DRAM specification syntax of Ramulator 2.0 is concise and human-readable, facilitating easy modifications and extensions. Ramulator 2.0 implements a library of reusable templated lambda functions to model the functionalities of DRAM commands to simplify the implementation of new DRAM standards, including DDR5, LPDDR5, HBM3, and GDDR6. We showcase Ramulator 2.0's modularity and extensibility by implementing and evaluating a wide variety of RowHammer mitigation techniques that require different memory controller design changes. These techniques are added modularly as separate implementations without changing any code in the baseline memory controller implementation. Ramulator 2.0 is rigorously validated and maintains a fast simulation speed compared to existing cycle-accurate DRAM simulators.