Innovative Recovery Strategy for MFIS-FeFETs at Optimal Timing With Robust Endurance: Fast-Unipolar Pulsing (100 ns), Nearly Zero Memory Window Loss (0.02%), and Self-Tracking Circuit Design

• Published in: IEEE transactions on electron devices Vol. 71; no. 5; pp. 3371 - 3376
• Main Authors: Wu, Cheng-Hung, Liu, Jay, Zheng, Xun-Ting, Chuang, Han-Fu, Tseng, Yi-Ming, Kobayashi, Masaharu, Su, Chun-Jung, Hu, Vita Pi-Ho
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuit design; Endurance; Fatigue; FeFETs; ferroelectric field-effect transistors (FeFETs); Ferroelectric materials; Ferroelectricity; Field effect transistors; interface optimization; Iron; nonvolatile; Passivation; Plasma measurements; Plasmas; recovery; Semiconductor devices; Timing; Tracking
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2024.3377191

This work systematically demonstrates a novel recovery scheme for metal-ferroelectric-insulator-semiconductor (MFIS) ferroelectric field-effect transistor (FeFET) memory arrays involving device fabrication, memory operation, and circuit integration. For the first time, the timing to initiate recovery to prolong the endurance of FeFETs is studied. A 100-ns fast-unipolar pulsing (FUP) recovery treatment at optimized timing is exhibited, significantly extending endurance cycles by a factor of <inline-formula> <tex-math notation="LaTeX">10^{{2}} </tex-math></inline-formula>, together with a nearly zero loss (0.02%) in memory window (MW) per recovery period and a reduced MW fluctuation. An ultralow recovery-induced time loss ratio of <inline-formula> <tex-math notation="LaTeX">5\times 10^{-{5}} </tex-math></inline-formula>% is achieved. Based on the developed scheme, we propose a self-tracking recovery circuit design utilizing current-mode memory sensing to monitor the degree of fatigue and automatically trigger the recovery operation.