Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI

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Bibliographic Details
Published inSolid-state electronics Vol. 117; pp. 185 - 192
Main Authors Taco, Ramiro, Levi, Itamar, Lanuzza, Marco, Fish, Alexander
Format Journal Article
LanguageEnglish
Published 01.03.2016
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ISSN:0038-1101
DOI:10.1016/j.sse.2015.11.013