Vertical AND-Type Flash Synaptic Cell Stack for High-Density and Reliable Binary Neural Networks

• Published in: IEEE electron device letters Vol. 45; no. 7; pp. 1369 - 1372
• Main Authors: Kim, Jangsaeng, Im, Jiseong, Oh, Seongbin, Shin, Wonjun, Jung, Gyuweon, Lee, Sung-Tae, Lee, Jong-Ho
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.07.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: binary neural networks (BNNs); Dynamic range; Fabrication; Flash memory (computers); Flash memory cells; Floors; High density; Logic gates; Misalignment; Neural networks; neuromorphic; one-shot patterning; Polysilicon; Reliability; source/drain sharing; synaptic device; Vertical AND-type (V-AND) flash memory
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2024.3401399

A vertical AND-type (V-AND) cell stack consisting of flash memory cells is proposed and fabricated for hardware-based binary neural networks (BNNs). Low-power operation is possible with a semicircular poly-Si channel surrounded by a single word-line. In each floor, two cells facing each other along the long axis of a single channel hole share a source/drain, greatly improving cell density and making it suitable for high-density BNNs. The fabricated V-AND flash memory cells show a high on/off current ratio (<inline-formula> <tex-math notation="LaTeX">\gt 10^{{5}}\text {)} </tex-math></inline-formula>, sub-pA off current, and large dynamic range (<inline-formula> <tex-math notation="LaTeX">\gt 10^{{4}}\text {)} </tex-math></inline-formula>. One-shot patterning of channel holes and isolation trenches minimizes loss of uniformity due to misalignment. The proposed BNN using synaptic properties measured from fabricated V-AND cells achieves high accuracy (87.82% for the CIFAR-10 dataset).