High-Performance Chip Design with Parallel Architecture for Magnetic Field Imaging System

• Published in: IEEE transactions on instrumentation and measurement Vol. 73; p. 1
• Main Authors: Lin, Ming-Yi, Hsieh, Sheng-Hsien, Chen, Ching-Han, Lin, Chun-Hung
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Computer architecture; Data processing; Data transmission; Field programmable gate arrays; Magnetic field imaging; Magnetic field sensor array; Magnetic fields; Magnetoresistance; Magnetoresistivity; nondestructive testing (NDT); Parallel architecture and algorithm; Parallel processing; Sensor arrays
• ISSN: 0018-9456; 1557-9662
• DOI: 10.1109/TIM.2023.3334351

To address the limitations of typical coil detection systems and enhance the performance of traditional magnetic field imaging systems, we propose a magnetic field imaging system that uses a 4 × 4 array of anisotropic magnetoresistance (AMR) sensors. The core controller of the proposed system was designed using a pipelined parallelization algorithm and implemented on a high-speed field-programmable gate array in a fully hardware-based architecture. The designed magnetic field imaging system can achieve parallel acquisition of magnetic field components from the 16-channel AMR sensor array, parallel data processing, parallel data transmission, and parallel computations in a single cycle of only 4 ms. Compared with typical detection systems, the proposed solution not only exhibits superior performance but can also provide dynamic visual representations of sensed information.