Curvilinear Standard Cell Design for Semiconductor Manufacturing

• Published in: IEEE transactions on semiconductor manufacturing Vol. 37; no. 2; pp. 152 - 159
• Main Authors: Kim, Ryoung-Han, Hwang, Soobin, Oak, Apoorva, Shirazi, Yasser, Chang, Hsinlan, Yang, Kiho, Mirabelli, Gioele
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adaptive optics; Algorithms; B spline functions; Curvilinear design; Design; design rule; design rule check; Design standards; Electronic design automation; gds; Manufacturability; metal layer; Metals; optical proximity correction; Optical sensors; Photolithography; Pins; Production costs; Routing; Shape; Shape optimization; standard cell; via layer; Voronoi graphs
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/TSM.2024.3362900

Curvilinear design was applied to standard cell layout to improve electrical characteristics and reduce manufacturing costs. Its implementation was intelligently co-optimized with 1-D Manhattan shapes and photolithography process to preserve the standard cell area equivalent to that of 1-D Manhattan-only designs. B-spline curve representation was employed to realize the curvilinear design. Curvilinear pathfinding was carried out through the Voronoi diagram to find the optimum routing path, and the A* routing algorithm to determine the shortest path. In the curvilinear-designed standard cells, the majority of standard cells exhibited reduced total metal length, decreased number of vias, and eliminated the need for an extra metal layer when compared to 1-D Manhattan-only standard cell designs. Manufacturability of curvilinear designs was evaluated, and potential solutions are proposed in the context of design rule, design rules check (DRC) and optical proximity correction (OPC). DRC and OPC were carried out within the currently employed electronic design automation (EDA) tools to verify the curvilinear designs.