A Variable Speed Induction Motor Drive With 24-Stepped Voltage Waveform Throughout Modulation Range

• Published in: IEEE transactions on industrial electronics (1982) Vol. 71; no. 2; pp. 1 - 9
• Main Authors: Surana, Prashant, Gopakumar, K., Umanand, Loganathan, Rajashekara, Kaushik, Franquelo, Leopoldo Garcia
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Capacitors; Electric potential; Harmonic analysis; High power drives; Higher harmonics; Induction motor drives; Induction motors; Inverters; Modulation; Multi-level inverter; Multilevel inverters; Phase current; Polygonal space vector structure; Polygons; Power harmonic filters; Pulse width modulation; Switches; Total harmonic distortion; Variable speed drives; Voltage; Waveforms
• ISSN: 0278-0046; 1557-9948
• DOI: 10.1109/TIE.2023.3260354

Multi-level inverters produce low order harmonics in over-modulation region, which can be eliminated by generating polygonal space vector structure. A variable speed induction motor drive to generate 24-stepped voltage waveform throughout modulation range is proposed in this article. An open-end winding configuration induction motor (OEIM) is fed with primary and secondary inverter from both the ends of OEIM and generates a 24-stepped phase voltage. The proposed scheme also produces 96-stepped phase voltage waveform at extreme modulation index with highly suppressed higher order harmonics and excellent quality phase voltage. The motor terminal sees a 24-stepped waveform at all speeds, devoid of low order harmonics up to <inline-formula><tex-math notation="LaTeX">19^{th}</tex-math></inline-formula> order. The scheme does not require vector timing calculation due to availability of highly dense 24-sided polygonal structure. Primary and secondary inverters are derived by cascading flying capacitor and CHB cells. Experimental verifications are performed on in-house developed laboratory prototype. Motor phase voltage and phase current waveforms during steady state and transient conditions justifies performance of the proposed scheme. Dynamic performance and floating capacitors voltage balancing method are verified by experimental results.