Improved MEOL and BEOL Parasitic-Aware Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet Transistor

• Published in: IEEE transactions on electron devices Vol. 69; no. 2; pp. 462 - 468
• Main Authors: Sun, Yabin, Wang, Meng, Li, Xianglong, Hu, Shaojian, Liu, Ziyu, Liu, Yun, Li, Xiaojin, Shi, Yanling
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Back-end-of-line (BEOL); Capacitance; Circuits; compact model (CM); Design optimization; design technology co-optimization (DTCO); Field effect transistors; gate-all-around nanosheet field effect transistor (GAA-NSFET); Integrated circuit modeling; Inverters; Logic gates; Mathematical analysis; middle-end-of-line (MEOL); Nanosheets; Nodes; Optimization; parasitic extraction; Power consumption; Reduction; Resistance; Semiconductor devices; Transistors

In this article, an improved parasitic-aware design technology co-optimization (DTCO) for gate-all-around nanosheet field effect transistor (GAA-NSFET) at 3 nm node is proposed. The presented DTCO flow owns two distinct features. First, a novel de-embedding strategy is designed to avoid the repeated...