Improved MEOL and BEOL Parasitic-Aware Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet Transistor

• Published in: IEEE transactions on electron devices Vol. 69; no. 2; pp. 462 - 468
• Main Authors: Sun, Yabin, Wang, Meng, Li, Xianglong, Hu, Shaojian, Liu, Ziyu, Liu, Yun, Li, Xiaojin, Shi, Yanling
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Back-end-of-line (BEOL); Capacitance; Circuits; compact model (CM); Design optimization; design technology co-optimization (DTCO); Field effect transistors; gate-all-around nanosheet field effect transistor (GAA-NSFET); Integrated circuit modeling; Inverters; Logic gates; Mathematical analysis; middle-end-of-line (MEOL); Nanosheets; Nodes; Optimization; parasitic extraction; Power consumption; Reduction; Resistance; Semiconductor devices; Transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2021.3135247

In this article, an improved parasitic-aware design technology co-optimization (DTCO) for gate-all-around nanosheet field effect transistor (GAA-NSFET) at 3 nm node is proposed. The presented DTCO flow owns two distinct features. First, a novel de-embedding strategy is designed to avoid the repeated calculation of gate-source/drain contact capacitance. Second, the parasitic resistance of the middle-end-of-line (MEOL) and back-end-of-line (BEOL) is accurately extracted, combing the front-end-of-line (FEOL) simulation and the calculation of MEOL/BEOL equivalent interconnect length. The power, performance, and area (PPA) of the benchmark circuit [15-stage ring oscillator (RO)] are collaboratively optimized. Considering the limitation of contacted gate pitch (CGP) and the process effects, the compromise of structure parameters is studied. GAA-NSFET architecture with 48% reduction in power consumption, 26% increase in speed, and 46% reduction in area is achieved, satisfying the scaling requirement from 5 to 3 nm node. All data here provide an optimization and design foundation for GAA-NSFET in future 3 nm technology node.