Vertical Writes: Closing the Throughput Gap between Deeply Scaled STT-MRAM and DRAM

• Published in: IEEE computer architecture letters Vol. 17; no. 2; pp. 151 - 154
• Main Authors: Ipek, Engin, Longnos, Florian, Shihai Xiao, Wei Yang
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.07.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Computer architecture; Computer memory; Decoding; Dynamic random access memory; Endurance; Memory systems; Microprocessors; non-volatile memories; Rams; Random access memory; STT-MRAM; Switches; Switching; Throughput; Writing
• ISSN: 1556-6056; 1556-6064
• DOI: 10.1109/LCA.2018.2820027

STT-MRAM is a second generation MRAM technology that addresses many of the scaling problems of earlier generation magnetic RAMs, and is a promising candidate to replace DRAM due to its high operational speed, scalable energy characteristics, and high write endurance. However, making the density of STT-MRAM competitive with that of DRAM while maintaining DRAM-like write throughput has proven challenging. Reducing the area of an STT-MRAM cell requires decreasing the width of the cell access transistor, which lowers the magnitude of the switching current supplied to the storage element during writes, and significantly hampers the switching speed. Consequently, write throughput constitutes a fundamental performance bottleneck for memory systems built from deeply scaled, dense STT-MRAM cells. This paper introduces vertical writes, a new technique that improves the write throughput of memory systems built from high-density STT-MRAM. Vertical writes exploit the observation that once the switching voltage has been applied across the bitlines and and sourcelines in an STT-MRAM array, it is possible to initiate the write operation for additional cells that are attached to the same column by simply turning on the corresponding wordlines. By leveraging the ability to write a 0 or a 1 to multiple cells at once, vertical writes improve average system performance by 21 percent, and enable an STT-MRAM based system to come within 5 percent of the performance of a DRAM based system.