Embedding graphs in books: a layout problem with applications to VLSI design

• Published in: SIAM journal on algebraic and discrete methods Vol. 8; no. 1; pp. 33 - 58
• Main Authors: CHUNG, F. R. K, THOMSON LEIGHTON, F, ROSENBERG, A. L
• Format: Journal Article
• Language: English
• Published: Philadelphia Society for Industrial and Applied Mathematics 1987
• Subjects: Combinatorics; Combinatorics. Ordered structures; Computer science; Exact sciences and technology; Fault tolerance; Graph theory; Graphs; Laboratories; Mathematics; Sciences and techniques of general use; Layout problem; Graph theory; Graph construction; Circuit synthesis; Multilayered printed circuit board; Planar graph
• ISSN: 0196-5212; 0895-4798; 2168-345X; 1095-7162
• DOI: 10.1137/0608002

We study the graph-theoretic problem of embedding a graph in a book with its vertices in a line along the spine of the book and its edges on the pages in such a way that edges residing on the same page do not cross. This problem abstracts layout problems arising in the routing of multilayer printed circuit boards and in the design of fault-tolerant processor arrays. In devising an embedding, one strives to minimize both the number of pages used and the "cutwidth" of the edges on each page. Our main results (1) present optimal embeddings of a variety of families of graphs; (2) exhibit situations where one can achieve small pagenumber only at the expense of large cutwidth; and (3) establish bounds on the minimum pagenumber of a graph based on various structural properties of the graph. Notable in the last category are proofs that (a) every $n$-vertex $d$-valent graph can be embedded using $O( dn^{1/ 2} )$ pages, and (b) for every $d > 2$ and all large $n$, there are $n$-vertex $d$-valent graphs whose pagenumber is at least \[ \Omega \left( \frac{n^{1/ 2 - 1/d}}{\log^2 n} \right). \]