A 1.2-W single-chip MPEG2 MP@ML video encoder LSI including wide search range (H/spl plusmn/288, V:/spl plusmn/96) motion estimation and 81-MOPS controller

An MPEG2 MP@ML video encoder large-scale integrated circuit (LSI) has been developed including an 81 MOPS controller and motion estimator. By using two adaptive algorithms, a wide motion-estimation search area (/spl plusmn/288 pixels horizontal and /spl plusmn/96 pixels vertical) was achieved with c...

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 33; no. 11; pp. 1765 - 1771
Main Authors Ogura, E., Takashima, M., Hiranaka, D., Ishikawa, T., Yanagita, Y., Suzuki, S., Fukuda, T., Ishii, T.
Format Journal Article
LanguageEnglish
Published IEEE 01.11.1998
Subjects
Adaptive algorithm
Circuits
CMOS technology
Computer architecture
Energy consumption
Large scale integration
Motion control
Motion estimation
Pipelines
SDRAM
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Summary:An MPEG2 MP@ML video encoder large-scale integrated circuit (LSI) has been developed including an 81 MOPS controller and motion estimator. By using two adaptive algorithms, a wide motion-estimation search area (/spl plusmn/288 pixels horizontal and /spl plusmn/96 pixels vertical) was achieved with computation complexity of only 0.5% (20 GOPS) of full search block-matching algorithm. By using this expanded motion-estimation search area, there is a significant improvement in picture quality for coding fast motion sequences. The power consumption was reduced by using an efficient pipeline architecture and optimizing the circuitry, especially in the motion-estimation block and the data transfers for the external SDRAM. The 13.7/spl times/12.4 mm/sup 2/, 4.5-M transistor device using 0.4-/spl mu/m CMOS technology dissipates 1.2 W at 3.3 V.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.726574