Yield Learning Methodologies and Failure Isolation in Ring Oscillator Circuit for CMOS Technology Research

We detail the use of ring oscillators (ROs) for yield learning during the research phase of a CMOS technology generation. Failing circuits are located and classified based on electrical analysis of ROs and FETs (Field Effect Transistor) wired out from RO environments. Based on electrical data and bi...

Full description

Saved in:
Bibliographic Details
Published inIEEE transactions on semiconductor manufacturing Vol. 32; no. 4; pp. 393 - 399
Main Authors Chan, Victor, Cheng, K., Greene, A., Levin, T. M., Teehan, S., Karve, G., Guo, D., Bergendahl, M., Lea, D., Strane, J. S., Austin, B., Boye, C., Mattam, S., Choi, S., Gaul, A.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.11.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Arrays
Circuits
CMOS
Field effect transistors
Gate leakage
Integrated circuit interconnections
integrated circuit yield
Inverters
Learning
Logic gates
MOSFET circuits
Oscillators
research and development
Ring oscillator
Ring oscillators
Semiconductor devices
Online AccessGet full text

Cover

More Information
Summary:We detail the use of ring oscillators (ROs) for yield learning during the research phase of a CMOS technology generation. Failing circuits are located and classified based on electrical analysis of ROs and FETs (Field Effect Transistor) wired out from RO environments. Based on electrical data and binning methods, we improve detection and classification fault methodologies and form a yield detractor pareto. Inline defect monitoring can help to estimate RO yield and is essential in CMOS technology research.
ISSN:0894-6507
1558-2345
DOI:10.1109/TSM.2019.2945696