Generating Cyclic-Random Sequences in a Constrained Space for In-System Validation
The constrained-random methodology is widely used during the pre-silicon verification of very-large scale integrated circuits. Recently, research efforts have been made to support the application of constrained-random patterns during the post-silicon validation stage. In this paper, we present a new...
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Published in | IEEE transactions on computers Vol. 65; no. 12; pp. 3676 - 3686 |
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Main Authors | , |
Format | Journal Article |
Language | English |
Published |
New York
IEEE
01.12.2016
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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