Generating Cyclic-Random Sequences in a Constrained Space for In-System Validation

• Published in: IEEE transactions on computers Vol. 65; no. 12; pp. 3676 - 3686
• Main Authors: Xiaobing Shi, Nicolici, Nicola
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Constrained-random stimuli generation; cyclic-random patterns; Integrated circuits; Methodology; post-silicon validation; Prototypes; Random processes; Signal generators; Software; Software algorithms; System-on-chip; Verification; Very large scale integration
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2016.2560840

The constrained-random methodology is widely used during the pre-silicon verification of very-large scale integrated circuits. Recently, research efforts have been made to support the application of constrained-random patterns during the post-silicon validation stage. In this paper, we present a new method, including both software algorithms and on-chip hardware structures, for in-system constrained-random generation of stimuli sequences that are uniformly distributed. More specifically, we facilitate in-system application of constrained-random sequences that are cyclic-random, i.e., all the valid values from the user-constrained space are generated only once before the entire sample space is exhausted. While software simulation environments commonly support this feature, e.g., randc in SystemVerilog, to the best of our knowledge this is the first time it is shown how such feature can be ported to hardware environments.