Impact of Dielectrics in SOI FinFET for Lower Power Consumption in Punch-through Current-based Local Thermal Annealing

Impact of device geometric structures and materials is discussed to improve power efficiency of punch-through current based electro-thermal annealing (ETA). Various sensitivities that affect device temperature during ETA are extracted and compared. Then, dielectric engineering in terms of thermal co...

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Bibliographic Details
Published inJournal of semiconductor technology and science Vol. 21; no. 3; pp. 222 - 228
Main Authors Cha, Dong-Woo, Park, Jun-Young
Format Journal Article
LanguageEnglish
Published 대한전자공학회 01.06.2021
Subjects
전기공학
punch-through
Annealing
FinFET
reliability
hot-carrier injection (HCI)
logic transistors
dielectric
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Summary:Impact of device geometric structures and materials is discussed to improve power efficiency of punch-through current based electro-thermal annealing (ETA). Various sensitivities that affect device temperature during ETA are extracted and compared. Then, dielectric engineering in terms of thermal conductivity and thermal isolation is suggested for better power management. Finally, time-dependent characteristics with various thicknesses of buried dielectric layer are discussed to improve annealing speed. As a result, the contents of this paper provide a guide to better application of ETA. KCI Citation Count: 1
ISSN:1598-1657
2233-4866
DOI:10.5573/JSTS.2021.21.3.222