Optimization of SiC:P Raised Source Drain Epitaxy for Planar 20nm Fully Depleted SOI MOSFET Structures

• Published in: ECS transactions Vol. 50; no. 9; pp. 533 - 542
• Main Authors: Loubet, Nicolas, Nagumo, Toshiharu, Adam, Thomas, Liu, Qing, Raymond, Mark, Cheng, Kangguo, Khakifirooz, Ali, Zhu, Zhengmao, Khare, Prasanna, Paruchuri, Vamsi K., Doris, Bruce, Sampson, Ron
• Format: Journal Article
• Language: English
• Published: 15.03.2013
• ISSN: 1938-5862; 1938-6737
• DOI: 10.1149/05009.0533ecst

This paper will focus on the capability of a low-temperature cyclical deposition/etch (CDE) epitaxy process based on Si2H6 to fabricate SiCP films exhibiting very-high, electrically-active P and C concentrations with fast growth rates. This process will be characterized on blanket wafers first and optimized for raised source/drain applications in planar FDSOI technology featuring 20nm design rules. Low temperature drive-in anneal in combination with high phosphorus doping was employed leading to best resistivity values of 0.3 mΩ.cm for SiP and 0.6 mΩ.cm for SiC2%P. We will show that increasing the phosphorus concentration in the layers enables us to have the same transistor overlap after diffusion anneal for comparable resistivity with SiP films and improved carbon substitutionality. Best Ron values as low as 220Ω.μm will be reported, measured on 20nm gate length transistors in planar FDSOI technology with an optimized process.