Digital RF Transmitter With Single-Bit \Delta\Sigma M-Driven Switched-Capacitor RF DAC and Embedded Band Filter in 28-nm FD-SOI

• Published in: IEEE transactions on microwave theory and techniques Vol. 67; no. 7; pp. 3200 - 3209
• Main Authors: Marin, Razvan-Cristian, Frappe, Antoine, Stefanelli, Bruno, Cathelin, Philippe, Cathelin, Andreia, Kaiser, Andreas
• Format: Journal Article
• Language: English
• Published: IEEE 01.07.2019
• Subjects: 28-nm FD-SOI; all-digital transmitter; body bias; delta–sigma modulation (∆∑M); Finite impulse response filters; finite-impulse response digital-to-analog converter (FIR-DAC); finite-impulse response filter (FIR); Mixers; Power demand; Quantization (signal); Radio frequency; switched-capacitor (SC) DAC; Switches; Transmitters
• ISSN: 0018-9480; 1557-9670
• DOI: 10.1109/TMTT.2019.2897929

This paper presents a single-bit RF transmitter based on single-bit switched-capacitor RF digital-to-analog converters (DACs) embedded in an finite-impulse response (FIR) filter (FIR-DACs). The transmitter system comprises a single-bit quadrature delta-sigma modulator (<inline-formula> <tex-math notation="LaTeX">\Delta \Sigma \text{M} </tex-math></inline-formula>), a digital mixer, and a 109-tap RF FIR-DAC stage with a single external inductor, combining D-A conversion with discrete- and continuous-time filtering. The on-chip part of the FIR-DAC is built exclusively with CMOS inverters and metal-oxide-metal capacitors, which are implemented in the interconnect layers to propose a compact fully digital solution, suitable for advanced CMOS nodes. A method for canceling redundant switching in the FIR-DAC is proposed to reduce its complexity and power consumption. Combining discrete- and continuous-time filtering, the out-of-band quantization noise of the 1-bit RF signal is strongly attenuated below the level required by emission masks. The RF FIR-DAC prototype is implemented in a 28-nm FD-SOI CMOS technology with ten metal layers and occupies a total active area of only 0.047 mm 2 . The overall power consumption is 38 mW at 4.6-dBm peak output power, 900-MHz carrier frequency, and 1-V supply. FD-SOI body bias <inline-formula> <tex-math notation="LaTeX">V_{t} </tex-math></inline-formula> tuning is used to effectively correct mixing clock duty-cycle errors in order to perform precise high-frequency I/Q interleaving, which enables high image and local oscillator rejections. The resulting power consumption, surface, and performance of the measured prototype make the proposed circuits and concepts particularly appropriate for use in emerging Internet of Things (IoT) applications.