Gate-first high-k/metal gate DRAM technology for low power and high performance products
It is the first time that the high-k/metal gate technology was used at peripheral transistors for fully integrated and functioning DRAM. For cost effective DRAM technology, capping nitride spacer was used on cell bit-line scheme, and single work function metal gate was employed without strain techno...
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Published in | 2015 IEEE International Electron Devices Meeting (IEDM) pp. 26.6.1 - 26.6.4 |
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Main Authors | , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , |
Format | Conference Proceeding Journal Article |
Language | English |
Published |
IEEE
01.12.2015
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Subjects | |
Online Access | Get full text |
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Summary: | It is the first time that the high-k/metal gate technology was used at peripheral transistors for fully integrated and functioning DRAM. For cost effective DRAM technology, capping nitride spacer was used on cell bit-line scheme, and single work function metal gate was employed without strain technology. The threshold voltage was controlled by using single TiN metal gate with La2O3 and SiGe/Si epi technology. The optimized DRAM high-k/metal gate peripheral transistors showed current gains of 65%/55% and DIBL improvements of 52%/46% for nMOSFET and pMOSFET, respectively. The results in process yield, performance, and reliability characteristics of the technology on 4Gb DRAM have shown that the gate-first high-k/metal gate DRAM technology can be regarded as one of the major candidates for next-generation low power DRAM products. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Conference-1 ObjectType-Feature-3 content type line 23 SourceType-Conference Papers & Proceedings-2 |
ISSN: | 2156-017X |
DOI: | 10.1109/IEDM.2015.7409775 |