Hardware Implementation of Integration-and-Fire Neuron Circuit on FPGA and Performance Evaluation for Applications in Spiking Neural Network

• Published in: Journal of semiconductor technology and science Vol. 25; no. 2; pp. 123 - 127
• Main Authors: Lee, Yeji, Shah, Arati Kumari, Kang, Myounggon, Cho, Seongjae
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 01.04.2025
• Subjects: 전기공학
• ISSN: 2233-4866; 1598-1657; 1598-1657; 2233-4866
• DOI: 10.5573/JSTS.2025.25.2.123

In this paper, we present the hardware implementation and performance analysis of the digital equivalent of an integrate-and-fire (I&F) neuron model using the field-programmable gate array (FPGA) technology. Inspired by the human brain, the I&F neuron model is crucial for achieving energy-efficient neuromorphic systems. The digital implementation was performed on a Zynq multiprocessor system-on-chip (MPSoC) FPGA using the Xilinx Vivado Design Suite, replacing analog components with their digital counterparts. Simulation and implementation results demonstrated the ability of the model to accurately replicate the spiking behaviors of biological neurons while utilizing minimal FPGA resources. Specifically, the design used only 0.01% of the available lookup tables and flip-flops, ensuring a compact and efficient implementation. The total on-chip power consumption was measured to be 0.71 W, with a junction temperature of 25.7 ◦C. These results validate the functionality and performance of the digital I&F neuron model and highlight its potential for integration into fully CMOS-based spiking neural networks. The compact design of the model, combined with low power consumption, makes it a promising candidate for scaling into larger and more complex neuromorphic computing systems. KCI Citation Count: 0