A 1.0 V, 9.84 fJ/c-s FOM reconfigurable hybrid SAR-sigma delta ADC for signal processing applications

• Published in: Analog integrated circuits and signal processing Vol. 99; no. 2; pp. 261 - 276
• Main Authors: Adimulam, Mahesh Kumar, Srinivas, M. B.
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.05.2019; Springer Nature B.V
• Subjects: Circuits and Systems; CMOS; Electrical Engineering; Engineering; Foundries; Linearity; Noise levels; Nonlinearity; Power consumption; Reconfiguration; Signal processing; Signal,Image and Speech Processing; Matlab Simulink modeling; Re-configurability; Low area; Sigma delta ADC; Low power; Switched capacitor; Successive approximation ADC; Signal processing applications
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-019-01434-w

In this paper, a novel, low power, 16-bit, 9.84 fJ/conv-step FOM, reconfigurable, hybrid SAR-sigma delta ADC is presented. The ADC has been designed and implemented with two stages of programmable 4-bit SAR ADC followed by an 8-bit first order incremental sigma delta ADC. The resolution (which is reconfigurable), power and performance are controlled statically to get 12-bit, 14-bit, 16-bit operation. To minimize the power consumption, opamp turnoff technique is implemented between the stages. Mathematical modeling of the design is carried out using MATLAB SIMULINK. The ADC is fabricated in global foundries 180 nm CMOS process and results presented are those actually measured. In terms of performance, the IC has a differential non-linearity of ± 0.25 LSB, integral non-linearity of ± 0.51 LSB, signal-to-noise distortion ratio of 91.1 dB and spurious-free dynamic range of 99.4 dB. The Walden and Schreier figures of merit (FOM W and FOM S ) at 1.6 MHz sampling frequency are 9.84 fJ/conversion-step and 183.6 dB respectively. Power consumption is measured to be 478 µW @ 1.0 V supply voltage and the total core area is found to be 0.15 mm 2 .