OPTIMSM: FPGA hardware accelerator for Zero-Knowledge MSM

• Published in: IACR transactions on cryptographic hardware and embedded systems Vol. 2025; no. 2; pp. 489 - 510
• Main Authors: Pottier, Xander, De Ruijter, Thomas, Bertels, Jonas, Legiest, Wouter, Van Beirendonck, Michiel, Verbauwhede, Ingrid
• Format: Journal Article
• Language: English
• Published: Ruhr-Universität Bochum 04.03.2025
• Subjects: Elliptic Curve Cryptography; Hardware Acceleration; Multi-Scalar Multiplication; Zero-Knowledge Proof
• ISSN: 2569-2925; 2569-2925
• DOI: 10.46586/tches.v2025.i2.489-510

The Multi-Scalar Multiplication (MSM) is the main barrier to accelerating Zero-Knowledge applications. In recent years, hardware acceleration of this algorithm on both FPGA and GPU has become a popular research topic and the subject of a multi-million dollar prize competition (ZPrize). This work presents OPTIMSM: Optimized Processing Through Iterative Multi-Scalar Multiplication. This novel accelerator focuses on the acceleration of the MSM algorithm for any Elliptic Curve (EC) by improving upon the Pippenger algorithm. A new iteration technique is introduced to decouple the required buckets from the window size, resulting in fewer EC computations for the same on-chip memory resources. Furthermore, we combine known optimizations from the literature for the first time to achieve additional latency improvements. Our enhanced MSM implementation significantly reduces computation time, achieving a speedup of up to x12.77 compared to recent FPGA implementations. Specifically, for the BLS12-381 curve, we reduce the computation time for an MSM of size 224 to 914 ms using a single compute unit on the U55C FPGA or to 231 ms using four U55C devices. These results indicate a substantial improvement in efficiency, paving the way for more scalable and efficient Zero-Knowledge proof systems.