Evaluation and Analysis of Packet-Length Effect on Networks-on-Chip

The network-on-chip （NoC） design methodology is an important trend for large system-on-chip designs to reduce the bandwidth and power constraints in traditional synchronous bus architectures. In the design of packet-based NoC, the packet-length plays an important role in the NoC throughput, latency,...

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Bibliographic Details
Published inTsinghua science and technology Vol. 15; no. 3; pp. 288 - 293
Main Author 金德鹏 林世俊 苏厉 周郭飞 曾烈光
Format Journal Article
LanguageEnglish
Chinese
Published Elsevier Ltd 01.06.2010
Subjects
MP-SoC
network-on-chip
packet-length effect
system-on-chip
平均长度
网络分析
网络吞吐量
网络数据包
能源消费量
芯片设计
network-on-chip
packet-length effect
system-on-chip
MP-SoC
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Summary:The network-on-chip （NoC） design methodology is an important trend for large system-on-chip designs to reduce the bandwidth and power constraints in traditional synchronous bus architectures. In the design of packet-based NoC, the packet-length plays an important role in the NoC throughput, latency, and energy consumption. The appropriate NoC packet-length was selected based on simulation and analysis of the packet-length effect on NoC for variable average data block length （ADBL） configuration parameters. A trade-off curve among throughput, latency, and energy consumption was developed and shows that the optimum packet length increases as the ADBL increases.
Bibliography:11-3745/N
network-on-chip
TP393.08
packet-length effect
network-on-chip; system-on-chip; packet-length effect; MP-SoC
TS101.921
system-on-chip
MP-SoC
ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISSN:1007-0214
1878-7606
1007-0214
DOI:10.1016/S1007-0214(10)70063-8