Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory

With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n/sup -/ junction with n/sup +/ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robust...

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Bibliographic Details
Published inIEEE transactions on electronics packaging manufacturing Vol. 23; no. 4; pp. 246 - 254
Main Authors Ikehashi, T., Imamiya, K., Sakui, K.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.10.2000
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Circuit design
Circuit simulation
Circuits
CMOS process
Contact holes
Design methodology
Devices
Electronics packaging
Electrostatic discharge
Flash memory (computers)
Isolation technology
Large scale integration
MOS devices
MOSFET circuits
Protection
Robustness
Simulation
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Summary:With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n/sup -/ junction with n/sup +/ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:1521-334X
1558-0822
DOI:10.1109/6104.895068