Technology demonstration of a novel poly-Si nanowire thin film transistor

A simple process flow method for the fabrication of poly-Si nanowire thin film transistors（NW-TFTs） without advanced lithographic tools is introduced in this paper.The cross section of the nanowire channel was manipulated to have a parallelogram shape by combining a two-step etching process and a sp...

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Published inChinese physics B Vol. 25; no. 11; pp. 656 - 661
Main Author 刘立滨 梁仁荣 单柏霖 许军 王敬
Format Journal Article
LanguageEnglish
Published 01.11.2016
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Abstract A simple process flow method for the fabrication of poly-Si nanowire thin film transistors（NW-TFTs） without advanced lithographic tools is introduced in this paper.The cross section of the nanowire channel was manipulated to have a parallelogram shape by combining a two-step etching process and a spacer formation technique.The electrical and temperature characteristics of the developed NW-TFTs are measured in detail and compared with those of conventional planar TFTs（used as a control）.The as-demonstrated NW-TFT exhibits a small subthreshold swing（191 mV/dec）,a high ON/OFF ratio（8.5 × 10~7）,alow threshold voltage（1.12 V）,a decreased OFF-state current,and a low drain-induced-barrier lowering value（70.11 mV/V）.The effective trap densities both at the interface and grain boundaries are also significantly reduced in the NW-TFT.The results show that all improvements of the NW-TFT originate from the enhanced gate controllability of the multi-gate over the channel.
AbstractList A simple process flow method for the fabrication of poly-Si nanowire thin film transistors（NW-TFTs） without advanced lithographic tools is introduced in this paper.The cross section of the nanowire channel was manipulated to have a parallelogram shape by combining a two-step etching process and a spacer formation technique.The electrical and temperature characteristics of the developed NW-TFTs are measured in detail and compared with those of conventional planar TFTs（used as a control）.The as-demonstrated NW-TFT exhibits a small subthreshold swing（191 mV/dec）,a high ON/OFF ratio（8.5 × 10~7）,alow threshold voltage（1.12 V）,a decreased OFF-state current,and a low drain-induced-barrier lowering value（70.11 mV/V）.The effective trap densities both at the interface and grain boundaries are also significantly reduced in the NW-TFT.The results show that all improvements of the NW-TFT originate from the enhanced gate controllability of the multi-gate over the channel.
Author 刘立滨 梁仁荣 单柏霖 许军 王敬
AuthorAffiliation Tsinghua National Laboratory for Information Science and Technology,Institute of Microelectronics, Tsinghua University, Beijing 100084, China
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Notes A simple process flow method for the fabrication of poly-Si nanowire thin film transistors（NW-TFTs） without advanced lithographic tools is introduced in this paper.The cross section of the nanowire channel was manipulated to have a parallelogram shape by combining a two-step etching process and a spacer formation technique.The electrical and temperature characteristics of the developed NW-TFTs are measured in detail and compared with those of conventional planar TFTs（used as a control）.The as-demonstrated NW-TFT exhibits a small subthreshold swing（191 mV/dec）,a high ON/OFF ratio（8.5 × 10~7）,alow threshold voltage（1.12 V）,a decreased OFF-state current,and a low drain-induced-barrier lowering value（70.11 mV/V）.The effective trap densities both at the interface and grain boundaries are also significantly reduced in the NW-TFT.The results show that all improvements of the NW-TFT originate from the enhanced gate controllability of the multi-gate over the channel.
11-5639/O4
transistor demonstration drain lowering fabrication swing planar originate leakage etching
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