Technology demonstration of a novel poly-Si nanowire thin film transistor
A simple process flow method for the fabrication of poly-Si nanowire thin film transistors（NW-TFTs） without advanced lithographic tools is introduced in this paper.The cross section of the nanowire channel was manipulated to have a parallelogram shape by combining a two-step etching process and a sp...
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| Published in | Chinese physics B Vol. 25; no. 11; pp. 656 - 661 |
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| Main Author | |
| Format | Journal Article |
| Language | English |
| Published |
01.11.2016
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| Online Access | Get full text |
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| Summary: | A simple process flow method for the fabrication of poly-Si nanowire thin film transistors（NW-TFTs） without advanced lithographic tools is introduced in this paper.The cross section of the nanowire channel was manipulated to have a parallelogram shape by combining a two-step etching process and a spacer formation technique.The electrical and temperature characteristics of the developed NW-TFTs are measured in detail and compared with those of conventional planar TFTs（used as a control）.The as-demonstrated NW-TFT exhibits a small subthreshold swing（191 mV/dec）,a high ON/OFF ratio（8.5 × 10~7）,alow threshold voltage（1.12 V）,a decreased OFF-state current,and a low drain-induced-barrier lowering value（70.11 mV/V）.The effective trap densities both at the interface and grain boundaries are also significantly reduced in the NW-TFT.The results show that all improvements of the NW-TFT originate from the enhanced gate controllability of the multi-gate over the channel. |
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| Bibliography: | A simple process flow method for the fabrication of poly-Si nanowire thin film transistors（NW-TFTs） without advanced lithographic tools is introduced in this paper.The cross section of the nanowire channel was manipulated to have a parallelogram shape by combining a two-step etching process and a spacer formation technique.The electrical and temperature characteristics of the developed NW-TFTs are measured in detail and compared with those of conventional planar TFTs（used as a control）.The as-demonstrated NW-TFT exhibits a small subthreshold swing（191 mV/dec）,a high ON/OFF ratio（8.5 × 10~7）,alow threshold voltage（1.12 V）,a decreased OFF-state current,and a low drain-induced-barrier lowering value（70.11 mV/V）.The effective trap densities both at the interface and grain boundaries are also significantly reduced in the NW-TFT.The results show that all improvements of the NW-TFT originate from the enhanced gate controllability of the multi-gate over the channel. 11-5639/O4 transistor demonstration drain lowering fabrication swing planar originate leakage etching |
| ISSN: | 1674-1056 2058-3834 |
| DOI: | 10.1088/1674-1056/25/11/118504 |