(Invited) Monolithic Three-Dimensional Integrated Circuits: Process and Design Implications

Conventional three-dimensional integrated circuits (3D ICs) stack multiple dies vertically for higher integration density, shorter wirelength, smaller footprint, faster speed and lower power consumption. However, the through-silicon-vias (TSVs) in die-stacking based 3D ICs are large in size (>1um...

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Bibliographic Details
Published inECS transactions Vol. 61; no. 6; pp. 3 - 10
Main Authors Geng, Hui, Maresca, Luke, Cronquist, Brian, Or-Bach, Zvi, Shi, Yiyu
Format Journal Article
LanguageEnglish
Published The Electrochemical Society, Inc 19.03.2014
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Summary:Conventional three-dimensional integrated circuits (3D ICs) stack multiple dies vertically for higher integration density, shorter wirelength, smaller footprint, faster speed and lower power consumption. However, the through-silicon-vias (TSVs) in die-stacking based 3D ICs are large in size (>1um) and reduce the benefits that can be attained by the technology. In this paper, we will introduce a new fabrication process that facilitates monolithic 3D die integration and yields much smaller TSVs (~50 nm). We will also discuss various design benefits brought by the monolithic 3D IC technology.
ISSN:1938-5862
1938-6737
DOI:10.1149/06106.0003ecst