Low noise active loop filter for radar PLL applications

This paper presents a simple structure for a low noise active loop filter, designed in 28nm CMOS process. Design strategies are used for minimizing both thermal and flicker noise at critical frequencies around 1MHz for radar PLL applications. Results show an input referred noise of 2.81 nV/VHz @1MHz...

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Bibliographic Details
Published in2018 International Conference on IC Design & Technology (ICICDT) pp. 77 - 80
Main Authors Donno, Andrea, D'Amico, Stefano, Nonis, Roberto, Thurner, Peter
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2018
Subjects
1f noise
Active filters
active loop filter
CMOS analog integrated circuits
noise
operational amplifier
Passive networks
Phase locked loops
Phase noise
PLL
Radar
Thermal noise
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Summary:This paper presents a simple structure for a low noise active loop filter, designed in 28nm CMOS process. Design strategies are used for minimizing both thermal and flicker noise at critical frequencies around 1MHz for radar PLL applications. Results show an input referred noise of 2.81 nV/VHz @1MHz for the op-amp of the loop filter, with nominal conditions and 1.8 V power supply, occupying an area of 0.039mm 2 .
DOI:10.1109/ICICDT.2018.8399760