High-Voltage-Tolerant Level Converter for Embedded Complementary Metal--Oxide--Semiconductor Nonvolatile Memories
In this paper, a high-voltage-tolerant level converter for embedded complementary metal--oxide--semiconductor (CMOS) nonvolatile memories is proposed. The level converter circuit includes a high-voltage driver and a level shifter, which makes use of $1\times V_{\text{DD}}$ devices to generate $2\tim...
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| Published in | Japanese Journal of Applied Physics Vol. 51; no. 2; pp. 02BE08 - 02BE08-4 |
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| Main Authors | , |
| Format | Journal Article |
| Language | English |
| Published |
The Japan Society of Applied Physics
01.02.2012
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| Online Access | Get full text |
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| Summary: | In this paper, a high-voltage-tolerant level converter for embedded complementary metal--oxide--semiconductor (CMOS) nonvolatile memories is proposed. The level converter circuit includes a high-voltage driver and a level shifter, which makes use of $1\times V_{\text{DD}}$ devices to generate $2\times V_{\text{DD}}$ signals without overstress. In addition, it features one select signal to make the level converter have the tri-state. The high-voltage driver efficiently stacks two transistors to allow a voltage drop of $V_{\text{DD}}$ for each transistor, which helps maximize the driving ability. The level shifter using the cross-coupled structure with small metal--oxide--semiconductor (MOS) capacitors drives the high-voltage driver without the "preconditioning" process. The level converter implemented using the 0.35 μm CMOS process on the area of 0.002 mm 2 was measured at $V_{\text{DD}} = 3.5$ V to generate the output signal swinging from 0 to 7 V. |
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| Bibliography: | Application of level converter circuit used in the embedded nonvolatile memory. Level converter consisting of two circuit blocks. Circuits of high-voltage driver for the bit-line of memory cell. On/off state of the transistors of the driver: (a) when $V_{\text{out}}$ is $V_{\text{DDH}}$, (b) when $V_{\text{out}}$ is 0 V, (c) when $V_{\text{out}}$ is floated. Level shifter circuit to provide the three control signals (lsd, ls, and $V_{\text{ind}}$) for the driver. On/off state of the transistors of the level shifter when $V_{\text{in}}$ is $V_{\text{DD}}$. Simulated waveforms of the node voltages for the driver with the output capacitance of 0.5 pF at 50 MHz. Micrograph of the proposed level converter circuit. Measured input and output waveforms at 2 MHz. Measured waveforms with the floated output at 500 kHz. |
| ISSN: | 0021-4922 1347-4065 |
| DOI: | 10.1143/JJAP.51.02BE08 |