A Hardware Scheduler for Real Time Multiprocessor System on Chip

This paper presents the design and implementation of a low-power hardware scheduler for multiprocessor system-on-chips. The Pfair scheduling algorithm is considered with three different implementation schemes: replicated software scheduler running on each processor, single software scheduler running...

Full description

Saved in:
Bibliographic Details
Published in2010 23rd International Conference on VLSI Design pp. 264 - 269
Main Authors Gupta, N., Mandal, S.K., Malave, J., Mandal, A., Mahapatra, R.N.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.01.2010
Subjects
Delay
Energy consumption
Hardware
Hardware Pfair Scheduler
Low Power
Multiprocessing systems
Multiprocessor
Processor scheduling
Real time systems
Scheduling algorithm
Software performance
System-on-a-chip
Very large scale integration
Online AccessGet full text

Cover

More Information
Summary:This paper presents the design and implementation of a low-power hardware scheduler for multiprocessor system-on-chips. The Pfair scheduling algorithm is considered with three different implementation schemes: replicated software scheduler running on each processor, single software scheduler running on a dedicated processor and the proposed hardware scheduler. Experimental evaluation with benchmarks shows that the hardware scheduler outperforms the other two schemes in terms of energy consumption by an order of magnitude of 10 5 and scheduling delay by an order of magnitude of 10 3 .
ISBN:1424455413
9781424455416
ISSN:1063-9667
2380-6923
DOI:10.1109/VLSI.Design.2010.43