Differential Propagation Delay Measurement of RSFQ Library Cells Using Ring Oscillators

• Published in: IEEE transactions on applied superconductivity Vol. 32; no. 4; pp. 1 - 7
• Main Authors: Ravi, Jushya, Meher, Sukanya Sagarika, Sahu, Anubhav, Chonigman, Benjamin, Inamdar, Amol
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuit design; Converters; Critical current density; Current measurement; Delay; Delays; Design; Differential delay measurement; Electrical measurement; Frequency dividers; Frequency measurement; input broadcasting scheme; input/output multiplexing scheme; Integrated circuits; Libraries; Matching; Multiplexing; Oscillators; Parameters; Propagation; ring oscillator; Ring oscillators; Semiconductor device measurement; Simulation; timing characterization; Transmission line measurements; Voltage measurement
• ISSN: 1051-8223; 1558-2515
• DOI: 10.1109/TASC.2022.3149233

Performing comprehensive timing characterization of library cells and establishing their model-to-hardware correlation are essential for building robust integrated circuits and scaling circuit complexity. To measure the propagation delay of fabricated library cells, we have designed a differential delay measurement scheme using SFQ ring oscillators. The reference and design-under-test (DUT) rings are designed using circuit elements that are either common to both rings or are of nominally similar design, except for the DUT. By inserting a single pulse in the ring, the oscillation period is measured using two methods: (1) direct voltage measurement, and (2) frequency measurement using a frequency divider followed by an SFQ-to-DC converter. Subtracting delay of the two rings gives us the propagation delay of the DUT. A 1 cm by 1 cm chip and another 5 mm by 5 mm chip, incorporating stand-alone ring oscillator test structures for different library cells, have been fabricated in the MIT-LL SFQ5ee process. The chips also contain test circuits to validate two variants of the input/output multiplexing scheme that facilitate reducing the pads requirement. Two copies of a chip with fifteen DUTs were tested. The measured and simulated results for the voltage and frequency of the ring are compared. The simulations account for critical current density ( J c ) and sheet resistance (Rs) fabrication parameters. In addition, we have used the J c as a single free parameter to get a better matching with measurement results. For one of the chips, a 15% higher J c in simulations results in better matching with measured frequency results for all the DUTs. For example, the discrepancy between simulated and measured DUT ring frequency for the NOT cell was reduced from 19% to 1% when the J c was changed from nominal to 15% higher in simulations. Detailed measurement and simulation results for several DUTs are presented.