Bus Assignment Considering Flexible Escape Routing for Layer Minimization in PCB Designs

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 41; no. 8; pp. 2699 - 2713
• Main Author: Yan, Jin-Tai
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Bus assignment; Buses; Constraints; Costs; Design automation; escape routing; Fabrication; Heuristic algorithms; layer minimization; Minimization; PCB design; Pins; Routing; Upper bounds
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2021.3112882

It is necessary for cost consideration to minimize the number of used layers in a PCB design. Traditionally, the number of used layers outside components in bus assignment depends on the locations of the bus pins inside components in escape routing in a PCB design. In this article, the concept of introducing the flexible escape directions in escape routing is considered in bus assignment outside components in a PCB design. Clearly, the flexible consideration of the escape directions inside components can lead to the reduction on the number of used layers in bus assignment outside components. Given a set of buses on a set of components in a PCB design, based on the introduction of the flexible escape directions in escape routing and the construction of the possible bus connections in bus assignment, the two upper bounds of the layer numbers inside and outside components can be first computed. By eliminating the redundant bus connections for the given buses, an integrated algorithm can be further proposed to minimize the number of used layers in a PCB design. Based on the assignment constraints from the intersection relations inside components, the physical connections of the given buses can be assigned onto a minimal set of used layers. Compared with the two-phase algorithm using Yan's routing algorithm in direction-constrained rectangle escape routing and Yan's assignment algorithm in bus assignment, the experimental results show that our proposed integrated algorithm uses reasonable CPU time to reduce 32.1% of the layer number for ten tested examples in a PCB design on the average.