A high speed frontend electronics ASIC for multi-channel single gap RPC detector

• Published in: Journal of instrumentation Vol. 16; no. 7; p. P07042
• Main Authors: Sukhwani, Menka, Chandratre, V.B., Hari Prasad, K., Thomas, Megha
• Format: Journal Article
• Language: English
• Published: Bristol IOP Publishing 01.07.2021
• Subjects: Amplifiers; Analogue electronic circuits; Application specific integrated circuits; Channels; CMOS; CMOS readout of gaseous detectors; Dynamic stability; Electronics; Front-end electronics for detector readout; High speed; Input impedance; Neutrinos; Power consumption; Receivers & amplifiers; Resistive plate chambers
• ISSN: 1748-0221; 1748-0221
• DOI: 10.1088/1748-0221/16/07/P07042

This paper presents a high speed prototype frontend electronics (FEE) ASIC, designed to meet the readout requirements of ∼ 3.6 million channels of avalanche mode single-gap resistive plate chamber detectors of Iron Calorimeter experiment of India based Neutrino Observatory. This ASIC is a regulated cascode transimpedance pre-amplifier based octal amplifier-comparator FEE solution in 0.35 μm CMOS process. Two DC stabilization techniques, one for common mode and another for differential DC offset cancellation, have been incorporated in this ASIC to ensure amplifier baseline stability, uniform dynamic range and comparator overdrive across readout channels. This DC common mode control can also be used to trim the input impedance of regulated cascode pre-amplifier. The ASIC provides parallel LVDS outputs on external 100 Ω load for tracking and precision time-tagging. A multiplexed analog output is also provided through an on-chip 50 Ω cable driver for detector pulse profile analysis. The ASIC has total channel gain of ∼ 0.75 mV/fC for single ended inputs of both the polarities, intrinsic timing precision of ∼ 190 ps RMS and ∼ 100 ps RMS for input charge of 0.1 pC and beyond 0.3 pC respectively with total power consumption of 40 mW/channel.