FinFET SCR structure optimization for high-speed serial links ESD protection

An optimized SCR structure was proposed for high turn-on speed and low parasitic capacitance in FinFET CMOS process. Experimental results indicate that the proposed SCR structure delivers the best known results among the literatures (140mA/fF). By adopting the structure, ESD protection design for mu...

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Published in2016 IEEE International Reliability Physics Symposium (IRPS) pp. 6A-1-1 - 6A-1-6
Main Authors Li-Wei Chu, Yi-Feng Chang, Yu-Ti Su, Kuo-Ji Chen, Ming-Hsiang Song, Jam-Wem Lee
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2016
Subjects
Electrostatic discharges
FinFETs
Layout
Logic gates
Parasitic capacitance
Thyristors
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Summary:An optimized SCR structure was proposed for high turn-on speed and low parasitic capacitance in FinFET CMOS process. Experimental results indicate that the proposed SCR structure delivers the best known results among the literatures (140mA/fF). By adopting the structure, ESD protection design for multi Gb/s transceiver can be simply realized.
ISSN:1938-1891
DOI:10.1109/IRPS.2016.7574555