Enabling efficient rate and temporal coding using reliability‐aware design of a neuromorphic circuit

• Published in: International journal of circuit theory and applications Vol. 50; no. 12; pp. 4234 - 4250
• Main Authors: Picardo, Siona Menezes, Shaik, Jani Babu, Singhal, Sonal, Goel, Nilesh
• Format: Journal Article
• Language: English
• Published: Bognor Regis Wiley Subscription Services, Inc 01.12.2022
• Subjects: adaptation exponential integrate & fire (I&F) circuit; Analog circuits; BTI & HCI; Carrier injection; Circuit design; Circuit reliability; Degradation; Fault detection; neuromorphic circuits; Reliability aspects; reliability issues; reliability‐aware design
• ISSN: 0098-9886; 1097-007X
• DOI: 10.1002/cta.3395

Reliability aspects such as bias temperature instability (BTI) and hot carrier injection (HCI) affecting devices in advanced CMOS‐based technology have been the subject of active research in recent decades. Due to these reliability issues, various digital and analog circuits were investigated for degradation. However, circuit blocks like the neuron circuits of neuromorphic systems are not fully explored. This work is inclined toward examining the collective degradation impact of BTI and HCI due to aging in an adaptive exponential “integrate and fire” (I&F) model‐based, neuromorphic neuron circuit. Detailed degradation analysis of the stimulated neuron circuit aided in identifying possible mismatches/faults associated with neuron spikes. These factors could reduce the efficiency of the neuronal circuit by potentially affecting the transmission of information in a neuromorphic system. Various performance parameters were then derived to quantify the extent of circuit deterioration. The proposed reliability‐aware design aims to improve the circuit degradation through its effectiveness in alleviating the overall reliability impact. It demonstrates enhanced circuit operation in spike generation even after aging. The circuit performance is validated through simulations at “Time0” (pre‐degradation) and “Aged” (post‐degradation) neuron netlists, which is then compared with the proposed reliability‐aware circuit. This article proposes a reliability‐aware silicon neuron (SiN) circuit that can effectively mitigate the combined impact of reliability issues like bias temperature instability (BTI) and hot carrier injection (HCI) due to aging. SiN aging was found to degrade performance parameters pertaining to output spikes, which is measured through faulty spiking, excitatory postsynaptic potential (EPSP), and interspike interval (ISI) mismatches. Degradation of the performance parameters can result in information transmission inaccuracies in the neuromorphic system through rate and temporal coding techniques.