Experimental Validation of a Compact Pinhole Latent Defect Model for MOS Transistors

• Published in: IEEE transactions on electron devices Vol. 69; no. 9; pp. 4796 - 4802
• Main Authors: Gomez, Jhon, Xama, Nektar, Lootens, Dirk, Coyette, Anthony, Vanhooren, Ronny, Dobbelaere, Wim, Gielen, Georges
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Characterization; compact modeling; defect-oriented test; Defects; Fabrication; Integrated circuit modeling; Integrated circuits; latent defects; Logic gates; Metal oxide semiconductors; MOS; MOS devices; MOSFET; Pinhole defects; Pinholes; Semiconductor devices; Shape; Silicon; Transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2022.3191990

Currently, the semiconductor industry requires test escape levels that approach the ppb level for application domains, such as automotive. Such quality levels, however, can only be reached if latent defects are screened out, as they have become the major bottleneck in analog and mixed-signal IC testing. Latent defects can be activated using accelerated aging, but this procedure has several drawbacks. Most notably, activation can move latent defects to the product lifetime that, otherwise, would not even have expressed themselves. Therefore, methods are needed that allow the detection of these defects without using activation. Developing such methods, however, has been hampered by the lack of compact latent defect models that allow simulating circuits affected by this type of defect. This article alleviates this problem by experimentally validating a recently presented compact model for latent defects and establishing the practical range of model values that should be used in simulations. The experiments performed on a 0.35-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> technology consist of characterizing transistors containing latent defects that have been artificially introduced by etching pinholes in their gate. The measurement results corroborate that the drain current in transistors with defects increases with the area and depth of the defect, and that this behavior can be accurately modeled using an effective <inline-formula> <tex-math notation="LaTeX">{t}_{ox} </tex-math></inline-formula> value.