Input offset compensation scheme with reduced sensitivity to charge injection and leakage
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Published in | Electronics letters Vol. 42; no. 6; pp. 340 - 341 |
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Main Authors | , , , , |
Format | Journal Article |
Language | English |
Published |
London
Institution of Electrical Engineers
16.03.2006
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Subjects | |
Online Access | Get full text |
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Author | LOPEZ-MARTIN, A. J CARVAJAL, R. G RAMIREZ-ANGULO, J GARIMELLA, L. M. K GARIMELLA, A |
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Keywords | Arithmetic circuit Integrated circuit testing Input signal Divider Integrated circuit |
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References | 10.1049/el:20064320_r1 Ramírez-Angulo (10.1049/el:20064320_r3) 1995; 42 10.1049/el:20064320_r2 Ramírez-Angulo (10.1049/el:20064320_r4) 2001; 48 |
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SubjectTerms | Applied sciences Circuit properties Design. Technologies. Operation analysis. Testing Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices |
Title | Input offset compensation scheme with reduced sensitivity to charge injection and leakage |
Volume | 42 |
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