A multiplier-accumulator macro for a 45 MIPS embedded RISC processor

This paper describes a high speed and area effective multiplier-accumulator for an embedded RISC processor. The point of architecture is to utilize a full adder array and the Booth's encoder twice in a cycle. The multiplier-accumulator executes one multiply-add operation (32 b multiplication fo...

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 31; no. 7; pp. 1067 - 1071
Main Authors Murakami, H., Yano, N., Ootaguro, Y., Sugeno, Y., Ueno, M., Muroya, Y., Aramaki, T.
Format Journal Article
LanguageEnglish
Published IEEE 01.07.1996
Subjects
Algorithm design and analysis
CMOS technology
Costs
Delay
Engines
Flip-flops
Information systems
Microelectronics
Reduced instruction set computing
Throughput
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Summary:This paper describes a high speed and area effective multiplier-accumulator for an embedded RISC processor. The point of architecture is to utilize a full adder array and the Booth's encoder twice in a cycle. The multiplier-accumulator executes one multiply-add operation (32 b multiplication followed by 64 b addition) per cycle at 56.5 MHz. The area is 2.35 mm/sup 2/ with 0.4 /spl mu/m CMOS technology.
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ISSN:0018-9200
1558-173X
DOI:10.1109/4.508224